The present invention relates to electronic circuits and methods of operation thereof and, more particularly, to phase locked loop (PLL) circuits and methods.
Clock frequencies used in digital circuits have increased with the rapid development of CMOS technology, as well as the steady improvement in electronic technology. A common approach to design of digital circuit is synchronous design, which typically uses a master clock. Clock requirements for high-speed digital systems have become increasingly stringent. These typically include low clock jitter, 50% duty cycle, low-voltage operation, low power consumption and compatibility with digital technology. Therefore, clock generating circuit design has become of significant importance.
Clock generating circuits may be classified as open loop and closed-loop. A typical open-loop clock generating circuit includes a crystal oscillator, an RC oscillator, an LC resonance circuit, a ring oscillator and a direct digital frequency synthesizer (DDFS). Generally speaking, a typical clock generating circuit without a reference frequency needs fine-tuning to obtain a desired frequency. In the above-mentioned oscillating circuits, the crystal oscillator, due to its higher Q-factor, can produce a low-jitter clock, so it is often used as a reference clock. The DDFS typically requires a reference clock to work out, via mathematical operations, the value of the desired frequency sampled by the reference clock. After digital-to-analog conversion of the digital amplitude sequence, the desired clock can be obtained through filtering. According to Nyquist sampling theory, the DDFS can synthesize a clock with a frequency less than half the reference frequency. However, due to physical constraints, the clock frequency generated by an open-loop clock generating circuit may not be high.
Closed-loop clock generating circuits include automatic frequency control (AFC) circuits and phase-locked loop (PLL) circuits. AFC circuits, which may be prone to frequency error, have generally declined in popularity, while PLL circuits have become a popular choice for frequency synthesis. PLLs may accurately synthesize a clock of very high speed, with frequency typically restricted only by the fabrication process used. A clock signal produced by a PLL can have good jitter performance. Special clocks can also be achieved using PLL. Examples of PLL applications include spread-spectrum clocks for reducing electromagnetic interference, multi-phase clocks, and clock data recovery.
Early PLLs used an analog multiplier as a phase discriminator. Because clock signals typically are square waves, filtering is often done to produce the sine waves, which may be very inconvenient. Moreover, difficulties in the design of analog multipliers can make the design of a PLL using an analog multiplier difficult.
A typical charge pump PLL uses a digital phase discriminator to compare square wave signals and can eliminate static phase contrast used in traditional PLLs. As digital phase discriminator design may be considered mature, designers may focus their attention on loop filter and voltage controlled oscillator (VCO) design. Charge pump PLLs typically can be highly integrated using digital CMOS technology.
Two types of oscillators that are widely used in charge pump PLLs are ring oscillators and LC oscillators. An LC oscillator, which requires on-chip inductance, may provide a clock with low phase noise. But the oscillating frequency may be limited to a small range. A ring oscillator, which may be compatible with digital technology, may provide wider frequency range. Ring oscillators are commonly used in PLLs to save cost.
Many digital chips today include one or more PLLs. The output frequencies of these PLLs may be different, and the requirements for the PLLs may not be the same. Design of such PLLs may require a lot of resources, manpower and time. A general-purpose or quasi-general-purpose PLL may, therefore, be desirable. A self-biased PLL with current steering digital to analog converter (IDAC) is an example of a general-purpose PLL, proposed in J. Maneatis et al., “Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL,” IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, February 2003, pp. 424-425. A potential disadvantage of such a PLL is its complexity.